Jelena Lalic, CERN: "Introduction to the Integrated Circuit Verification Process and RD53C Results"

Wednesday 18 Jan 2023, 12:00 → 13:00 US/Pacific

zoom

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https://lbnl.zoom.us/j/97903266602

 

Abstract: 

The Universal Verification Methodology (UVM) is a SystemVerilog-based methodology for IC design verification. We will discuss the fundamentals of the UVM, its key benefits, and reasons why it has become a de facto verification standard for complex digital designs. A framework used for the RD53C chip will be discussed and will illustrate the UVM concepts in more detail. Framework building blocks, functional tests, coverage collection, and the RD53C functional verification results will be addressed. SEE tolerance verification is an important part of the radiation-tolerant RD53C chip design. SEE verification methodology, including faultable nodes extraction and faults injection, will be presented. We will see how a SEE verification component was successfully used to identify SEE vulnerabilities and how they are fixed in the RD53C design.

UVM_AND_RD53_VER_ENV.pdf